Nuvotronics, Inc.

PolyStrata® PCB Integration Guide

Purpose

This document is intended to outline general guidelines when integrating PolyStrata® surface mount components onto a PCB. This includes footprint creation/import, matching compensation for PolyStrata® to transmission line, setting up paste and solder resist layers, and design for manufacturability rules to include in a design.

Table of Contents

  1. Footprint Import
  2. Footprint Creation
  3. Re‑tuning PolyStrata® to Co‑planar Waveguide Transition

Footprint Import

For all PolyStrata® SMT components, DXF drawings and native Altium libraries are available for importing into ECAD tools. Other formats may be available on request. Nuvotronics recommends importing the footprint using one of these provided formats for best results. Every ECAD tool will be slightly different with how DXFs are imported. However, the general procedure for importing DXFs is as follows:

  1. Open the DXF in your preferred ECAD tool.
  2. Assign layers from the DXF to the corresponding design layer:
Assigning DXF layers to design layers in the ECAD layer manager
Assigning DXF layers to design layers in the ECAD layer manager
  1. Pad Holes: only used on legacy parts, for alignment pins to the PCB.
  2. Top Layer: top copper and top keepouts. Filled copper appears as solid polylines; keepouts appear as dashed polylines.
  3. Top Paste: recommended solder paste pattern.
  4. Top Solder: top side solder‑resist negative.
  5. Via Holes: recommended via size/placement for isolation and matching.
  1. After import, the footprint should be a collection of polylines.
Footprint as imported — polyline boundaries and via reference circles
Footprint as imported — polyline boundaries and via reference circles

Each polyline represents the boundary edge of a fill. To finish the footprint, create a fill region inside each polyline boundary on the corresponding layers. For via placement, place the via in the center of the reference circles and set the annular ring size to the diameter of the reference.

  1. The result of the import, after fills and vias are completed:
    Completed footprint after fills and via placement
    Completed footprint after fills and via placement

Footprint Creation

Another approach to creating a footprint is using the Nuvotronics provided interface control drawing (ICD) with expansion design rules. An example of an ICD is provided below:

Example Interface Control Drawing (ICD) with SMT launch breakout detail
Example Interface Control Drawing (ICD) with SMT launch breakout detail

Ordinate dimensions of the PCB contact points are provided on the control drawing. Additionally, a breakout view of the SMT launch is provided to maintain the 50Ω reference plane at the contact point. The design procedure for creating the footprint is:

  1. Create pads/landing points based on the provided PolyStrata® geometry.
  2. Expand out the paste layer, copper layer, and solder resist by 1, 2, and 4 mil respectively:
    Paste, copper pad, and soldermask expansion — 1 / 2 / 4 mil respectively
    Paste, copper pad, and soldermask expansion — 1 / 2 / 4 mil respectively
  3. Add copper keepout around the RF launch to match ground geometry:
    Copper keepout around the RF launch — RF ground and RF signal detail
    There should be no copper fill between the center conductor and RF ground.

Re‑tuning PolyStrata® to Co‑planar Waveguide Transition

The CPWG transition provided by Nuvotronics is tuned to the PCB stackup outlined in the part’s corresponding datasheet. Several stackups may be used depending on the upper frequency range of the PolyStrata® part. Generally, the following 4-layer stackup using RO4350B dielectric is used unless otherwise noted:

4-layer PCB stackup diagram using RO4350B dielectric, showing top overlay, top solder, top plating and surface finish, L1 top layer, RO4350B core, L2 RF ground, RO4450F prepreg, L3 RF ground, RO4350B core, L4 bottom layer, and bottom solder, with a total thickness of 1.021mm plus or minus 10 percent

[1] These dielectrics may be FR4‑2116 for PCBAs that only use CPWG and thus have no RF traces in layers 3–4.

For any deviations from this stackup, the tuning stub will need to be adjusted to accommodate for board parasitics in the transition. The PolyStrata® RF port is designed to be nominal 50Ω. The footprint land pattern will have a small series inductance to accommodate for the parasitic capacitance in the transition from rectangular coax on the PolyStrata® to CPWG on the board:

RF tuning feature in the footprint land pattern
RF tuning feature in the footprint land pattern
For more information or assistance with this tuning feature, please reach out to your Nuvotronics representative to connect with Applications Engineering.