Design and Application Notes for PolyStrata® Die Packages

Construction

Packages are custom‑sized to MMIC dimensions to maximize substrate area and optimize RF performance.

Die Pedestal

• The die pedestal — where the die is placed on the substrate — is typically sized 100 µm larger than the die perimeter.
• To mitigate CTE mismatch with sensitive die, consider the die adhesive used or a die‑on‑carrier approach.
• Nuvotronics assumes the die is attached directly to the pedestal with epoxy or silver sintered paste. The step down from the RF wire bond surface to the die pedestal is 100 µm.

Bias / Passive Component Area

• Available for wire‑bondable components integrated inside the package, depending on die needs.
• Can be increased, reduced, or placed on both sides of the pedestal to meet die needs.
• Typical use case: size 1515 single‑layer, wire‑bondable 100 pF capacitors to filter gate and drain signals. Additional signal‑conditioning components would be located on the PCB, outside the package.

RF Wire Bond Launch

• Wire bond geometry is critical to achieving the desired performance — see the specific substrate datasheet for guidance.
• Standard gap between die edge and transition edge: 50 µm.

RF SMT Transition

RF package I/Os are designed and tuned with the PCB in mind. Application laminate material and thickness, as well as via size and placement, must match the design. Refer to the substrate datasheet and footprint file for correct board geometry.

DC SMT Transition

• DC pins are not as sensitive as RF I/Os.
• Internal pads are 260 µm in diameter and designed to accept wire bond interconnects.
• These pads feed through to leads on the bottom of the package.
• Quantity and location can be modified to meet die needs, including placement on any or all sides of the package.
• Minimum pitch between DC pins: 800 µm, with a ground pin in between.

Part Number & Serialization

Each package substrate carries a part number identifying the unique design, plus a serialization number identifying that part’s location on the wafer or panel.

Package Walls: Exterior & Interior

• The exterior wall runs around the perimeter of the substrate. Typical wall width is 330 µm to allow for various lid attach methods — functionally equivalent to the seal ring on LTCC or plastic packages.
• All parts contain a manufacturing feature (tether stubs) laser cut prior to delivery, necessary for batch processing. Discoloration around these features does not affect functionality.
• Substrate geometry varies between package families — refer to the datasheet or CAD models for specific dimensions.
• Interior walls can be implemented to create channelization and address cavity resonance issues.
• In addition to tether stubs, a 150 x 300 µm orientation pad is located on the exterior wall of the package.

Part Finish

• Wire‑bondable direct immersion gold (DIG), minimum 100nm thickness.
  • The DIG process yields a uniform gold finish across part surfaces. Underlying copper is fully covered, allowing for consistent wire‑bond or soldering with little part‑to‑part finish variation.
• Proper handling and care should be observed to preserve the gold finish and wire‑bondable surface — see Handling & Storage below.

Thermal Considerations

• Thermal performance is dominated by the die attach approach (epoxy, sintered silver, solder to carrier) and the thermal resistance of the board and thermal management approach used.
• The package body is entirely copper — including underneath the die pedestal — maximizing heat spreading and heat transfer area at the bottom of the package.
• For thermally demanding applications, pay special attention to thermal vias in the ground/heat‑transfer area of the package footprint. Effectiveness depends on via size, spacing, and type (e.g. copper‑filled), substrate thickness, thermal plane design, or use of an embedded copper coin or PCB cutout for direct heat‑sink contact.
• A fully detailed CAD model of the package can be provided on request to assist with thermal analysis.
• With a copper lid, heat can be removed effectively through the top of the package — thermal resistance to the lid is 6.12°C/W.
• Thermal resistance of a 5×5 mm substrate is 2.36°C/W, determined via FEA from the backside of the die to the bottom surface of the package, including a 25 µm‑thick silver sinter die attach interface.

Handling & Storage

Typical Environmental Test Results

Wire Bonding Guidelines

• Substrates are compatible with gold ribbon, wire, and ball bonding processes.
• Parts must be sufficiently secured during bonding on a heated stage. Consider part shape and bottom surface geometry when planning a securing method.
• Parts remain wire bondable after multiple thermal excursions through solder reflow (6 min @ 260°C) or ambient exposure, with bond strengths above MIL‑STD‑883 pull test requirements. Cleaning with argon plasma must be conducted prior to bonding.

Lid Attach Options

• Lids attach to the external wall using epoxy or solder. Laser sealing and seam sealing may be possible but have not been explored by Nuvotronics.
• Lid material can be metal or plastic. Account for potential cavity modes when considering lid options — an RF absorber may be required to mitigate resonance issues.
• A cavity‑style lid is needed if wire bond loop height is proud of the external package walls.

PCB Design

• Refer to the specific part datasheet for part‑specific PCB design needs.
• A recommended layout for each package is available on request, via DXF format, containing:
  • Part Keep Out — minimum allowable encroachment of neighboring components and board features
  • Vias — location and size of vias from top to the ground layer of the microstrip
  • Package Footprint — the physical bottom surface of the package that contacts the board
  • Top Copper — top layer copper pattern
  • Top Paste — recommended stencil opening
  • Top Mask — solder mask pattern
• Refer to notes on board thickness and material — crucial to achieving specified performance.
• Thermal vias can be placed anywhere underneath the package body, provided they don’t interfere with top‑layer pattern geometry or RF transition vias. The entire body of the package can be used for heat transfer.

SMT Guidelines

• Placement force should be kept to < 400 grams.
• PolyStrata Die Packages are compatible with all solder reflow profiles described in J‑STD‑020.